1. Field of the Invention
The present invention relates to a semiconductor device having a multi-layer interconnect metal structure made up of three or more layers and, in particular, to the layout of main power supply lines for a semiconductor device of multi-layer interconnect metal structure.
2. Description of the Related Art
FIG. 1 is a plan view showing a conventional multilayer interconnect pattern Reference numeral 1 denotes an IC chip whose power supplies V.sub.DD and GND are connected to a power supply pad 2 and ground pad 3, respectively, and are also connected to closed-loop patterns (power supply line patterns) 6 and 7, respectively, via a second metal layer (Al) 4 and first metal layer (Al) 5. The closed-loop patterns 6 and 7 are formed of the same material as that of the second metal layer (left-inclined hatched area in FIG. 1) in which case due consideration is paid to input/output signal lines 9, 10, and 11 coming from a logic block 8. The input/output signal lines 9, 10, and 11 coming from the logic block 8 are formed of the same material as the first metal layer (interconnect pattern without a hatched area) and provide a multi-level crossing relative to the power supply line patterns 6 and 7. Signal lines 9, 10, and 11 are connected to an input pad 12, output pad 13, and logic block 14, respectively.
In the conventional semiconductor device, elements, such as transistors, are not formed at a pattern area between an interconnect pad and a logic block, or at a pattern area between a logic block and another logic block, this being because the pattern areas are used as interconnect areas for power supply lines and signal lines. On the other hand, the pattern width of the power supply lines 6 and 7 needs be broadened due to a need for more current flow in which case the size of the chip 1 is increased, for example, due to an increase in the number of transistors in the chip 1 and hence an increase in dissipation current in the chip 1. Such an increase in the size of the chip 1 results in an increase in the size of the interconnect area between the pad and the logic block and between the logic blocks. This prevents an increase in the integration density of transistors and hence a reduction in the chip size. That is, even if the integration density of the transistors is to be increased, there is no significant decrease in the area taken up by the power supply lines; rather, an increase in the number of transistors results in an increase in the width of the power supply lines. Consequently, no substantial reduction in the chip size is possible.